1. Field of the Invention
The present invention relates to a semiconductor device such as a thin film transistor (TFT) used in an image sensor, a liquid crystal display device and an integrated circuit and a method for manufacturing the same.
2. Description of the Related Art
Recently, a performance of a large size device is improved by arranging thin film transistors (TFTs) in the device, and products which miniaturization is made by simplifying a peripheral circuit come onto the market. In particular, an active matrix manner in which the TFTs are each arranged to each liquid crystal pixel is applied to a large size liquid crystal display device used in a note book type or lap top type personal computer spread from about 1990, and such liquid crystal display device has superior characteristics as a display device. However, since its manufacturing process is complicated and it is expensive, it is desired to decrease its cost.
Until now, almost every TFTs used in the large size liquid crystal display device are formed by amorphous silicon in a product level. In the amorphous silicon TFT, its performance as a transistor is low. For example, an electron mobility is 10.sup.-2 to 10.sup.-3 times in comparison with that of a single crystalline silicon transistor. Therefore, it is required that a circuit for driving a TFT arranged in a pixel is arranged in an external by using an IC (integrated circuit) formed by signal crystalline silicon.
When a TFT formed by amorphous silicon is arranged in a pixel, It is necessary to set a wide channel width in order to obtain a sufficient driving speed by supplying a large current. However, if a channel width of the TFT arranged in the pixel is extended, an opening (appearance) rate required to obtain high display quality decreases. Since an amorphous silicon film and amorphous silicon nitride film has an electrical instability essentially, reliability for a long period cannot be obtained.
To solve above problem, it is expected that a TFT is formed by poly-crystalline silicon. In such TFT, an ON current value is several ten to one hundred times or more and has high reliability because of stability, in comparison with that of an amorphous silicon TFT. Further, since both of N-type and P-type transistors can be formed, a CMOS circuit can be constructed, so that consumption power can be reduced.
As described above, the poly-crystalline silicon TFT has superior characteristics. However, an OFF current value is large. Also, when a gate voltage is applied to an inverse bias side (negative (minus) side in an N-type TFT, and positive (plus) side in a P-type TFT), a current is increased. Further, when a drain voltage is increased, a drain current is markedly increased.
It is known that increase of a current in the inverse bias side can be prevented by forming an offset structure or an LDD (lightly doped drain) structure in a drain electrode side. In a conventional main method for forming an offset structure, after a gate electrode is patterned, a silicon oxide film is formed by a film formation method having a superior step coverage and then etched by an etching method having high anisotropy, to form a doping mask called a side wall or a spacer in sides of the gate electrode. Since the side wall is formed in both sides of the gate electrode in a conventional method, an offset region and a high resistance region are also formed in a source region side. Therefore, since these regions operate as a serial resistor in a TFT, an ON current reduces. In order not to form an offset region and a high resistance region in a source region side, photolithography process and ion implantation process each can be increased two times. However, by the increase of processes, a cost increases and a yield decreases.
When a MOS transistor which has SOI (Silicon on Insulator) structure and is formed by a single crystalline silicon in which an OFF current does not increase, such as a polycrystalline silicon TFT, does not include an offset structure and an LDD structure, an phenomenon that a drain current increases rapidly produces easily. If the transistor operates is performed in a bias state that such phenomenon produces, a threshold value may be shifted or an ON current may be decreased.
As described above, a TFT is desired that an OFF current and a current flowing between drain and source electrodes when a gate voltage of an inverse bias is applied is small, an ON current is sufficiently large, a drain current does not increase rapidly and reliability is high.
In order to obtain such TFT, it is desired that an offset structure or an LDD structure is formed in only drain region side. However, in a conventional method, since such TFT cannot be formed without largely increasing the number of processes, it is disadvantageous in a yield and a cost.